Banca de QUALIFICAÇÃO: ADELINO AFONSO FERNANES AVELINO

Uma banca de QUALIFICAÇÃO de MESTRADO foi cadastrada pelo programa.
STUDENT : ADELINO AFONSO FERNANES AVELINO
DATE: 18/10/2022
TIME: 09:00
LOCAL: Virtual: meet.google.com/ory-dtzo-aur
TITLE:

Elastic SDNoC model based on shortest paths

KEY WORDS:

Latency, Parallelism, Software-Defined Network-on-Chip, Network-
on-Chip.

PAGES: 50
BIG AREA: Ciências Exatas e da Terra
AREA: Ciência da Computação
SUBÁREA: Sistemas de Computação
SPECIALTY: Hardware
SUMMARY:

In this work, we developed a new network-on-chip architecture using software-
defined networks, this architecture proved to be robust and capable of improving
routing in a network-on-chip. The implementation consists of a software-defined
network-on-chip architectural model, exploring the parallelism of control mechanisms using Dijkstra’s algorithm to find the best path in packet routing
between switches. The approach proposes a significant improvement in communication latency by reducing the waiting time of packets in the controllers’
queue and exploring the network’s topological potential through the OpenFlow
protocol. The results obtained are promising. Using the Dijkstra algorithm and
increasing the number of cores makes it possible to optimize communication
latency in 100% of the cases compared to the XY algorithm.

COMMITTEE MEMBERS:
Presidente - 1694485 - MARCIO EDUARDO KREUTZ
Interna - 1882699 - MONICA MAGALHAES PEREIRA
Externo à Instituição - ALISSON VASCONCELOS DE BRITO - UFPB