Banca de DEFESA: HADLEY MAGNO DA COSTA SIQUEIRA

Uma banca de DEFESA de DOUTORADO foi cadastrada pelo programa.
STUDENT : HADLEY MAGNO DA COSTA SIQUEIRA
DATE: 27/03/2020
TIME: 08:00
LOCAL: Auditório I - DIMAp
TITLE:

Proposal of an high performance architecture for real-time systems.


KEY WORDS:

Precision-Timed Machines. Multicore, Coarse-Grained Reconfigurable Arrays, Cyber-Physical, Real-Time Systems.


PAGES: 104
BIG AREA: Ciências Exatas e da Terra
AREA: Ciência da Computação
SUBÁREA: Sistemas de Computação
SPECIALTY: Hardware
SUMMARY:

Precision-Timed Machines (PRET) are architectures intended for use in real-time and cyber-physical cyber systems. The main feature of these architectures is that they provide predictability and repeatability for real-time tasks, thus facilitating development, analysis, and testing of these systems. The state of the art, at the time of this writing, consists of processors based on the PRET concept. These processors explore thread-level parallelism by interleaving threads at a fine-grained level, i.e. at each clock cycle. This strategy provides good performance when there is parallelism at the thread level, but induces a low performance in the absence of this parallelism. In addition, the switching of threads to each clock cycle leads to high latency. This high latency can make it impossible performing tasks that require low latency. The present work contributes for the state of the art in two ways: first by presenting a proposal for a reconfigurable coarse-grain reconfigurable array based on the PRET concept. The proposed array is coupled to a PRET processor, providing support for accelerating important parts of an application. The array was designed in such a way that when coupled to the processor do not make the processor lose its original temporal properties. The second contribution of this thesis is the proposal and implementation of a multicore architecture. Each core is composed of a processor coupled to the proposedarray. Thus, this work seeks to present a high-performance architecture facing embedded real-time systems that have a high demand for performance such as avionics, for example. Results show that the proposed architecture is capable of providing acceleration of more than 10 times for some types of applications. In terms of area, synthesis results for FPGA show that each core occupies less than half of a processor running out of order. In addition, it has an area similar to other arrays used in low-power embedded systems.


BANKING MEMBERS:
Presidente - 1694485 - MARCIO EDUARDO KREUTZ
Interna - 1882699 - MONICA MAGALHAES PEREIRA
Externo ao Programa - 2140727 - GUSTAVO GIRAO BARRETO DA SILVA
Externo à Instituição - CESAR ALBENES ZEFERINO - UVI
Externo à Instituição - IVAN SARAIVA SILVA - UFPI
Notícia cadastrada em: 23/03/2020 10:49
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