Optimization of Irregular NoC Topology for Real-Time and Non-Real-Time Applications in Networks-on-Chip based MP-SoCs.

Network-on-Chip, Irregular Topology, Design Space Exploration.

With the evolution of multiprocessing architectures, Networks-on-Chip (NoCs) have become a viable solution for the communication subsystem. Since there are many possible architectural implementations, some use regular topologies, which are more common and easier to design. Others however, follow irregularities in the communication pattern, turning into irregular topologies. A good design space exploration can give us the configuration with better performance among all architectural possibilities. This work proposes a network with optimized irregular topology, where the communication is based on routing tables and a tool that seeks to perform this exploration through a Genetic Algorithm. The network proposed in this work presents heterogeneous routers (which can help with network optimization) and supports real-time and non real- time packets. The goal of this work is to find a network (or a set of networks), through the design space exploration, that has the best average latency and the highest percentage of packets that meet their deadlines.