Recent years have seen a dramatic increase in the importance of

Field-Programmable Gate Arrays as compute accelerators.  Companies such as

Amazon, IBM, Microsoft, and Baidu have started including FPGAs in their data centers aiming to accelerate their search engines. In the center of those applications are many machine learning algorithms, such as Support Vector Machines (SVMs). For FPGAs to thrive in this new role, the effective usage of FPGA resources is required. The project’s main goal is the parallel FPGA implementation of both the feed-forward phase of a Support Vector Machine as well as its training phase. The feed-forward phase (inference) is implemented using the polynomial kernel in a highly parallel way in order to obtain maximum throughput at the cost of some extra area. Moreover, the inference implementation is capable of computing both classification and regression using a single hardware. The training phase of the SVM is implemented using Sequential Minimal Optimization (SMO), which enables the resolution of a complex convex optimization problem using simple steps. The SMO implementation is also highly parallel and uses some acceleration techniques, such as the error cache. Moreover, the Hardware Friendly Kernel (HFK) is used in order to reduce the kernel's area, enabling the increase in the number of kernels per area. After the parallel implementation in hardware, the SVM is validated by simulation. Finally, analysis associated with the temporal performance of the proposed structure, as well as analysis associated with FPGA’s area usage are performed.