Banca de QUALIFICAÇÃO: DANIEL HOLANDA NORONHA

Uma banca de QUALIFICAÇÃO de MESTRADO foi cadastrada pelo programa.
DISCENTE : DANIEL HOLANDA NORONHA
DATA : 24/01/2017
HORA: 09:30
LOCAL: Auditório NPITI
TÍTULO:

Implementation of Support Vector Machines on FPGA

PALAVRAS-CHAVES:

Support Vector Machine, Sequential Minimal Optimization, FPGA.

PÁGINAS: 40
GRANDE ÁREA: Engenharias
ÁREA: Engenharia Elétrica
SUBÁREA: Circuitos Elétricos, Magnéticos e Eletrônicos
ESPECIALIDADE: Circuitos Eletrônicos
RESUMO:

The project’s main goal is the parallel FPGA implementation of both the feed-forward phase of a Support Vector Machine (SVM) as well as its trainning phase. The training phase of the SVM will be implemented using Sequential Minimal Optimization (SMO) and the kernel used will be the polynomial. After the parallel implementation in hardware, the SVM will be validated by simulation. Moreover, analysis associated with the temporal performance of the proposed structure, as well as analysis associated with FPGA’s, area will be performed.

MEMBROS DA BANCA:
Presidente - 1837240 - MARCELO AUGUSTO COSTA FERNANDES
Interno - 347628 - ADRIAO DUARTE DORIA NETO
Externo ao Programa - 347065 - JOSE ALBERTO NICOLAU DE OLIVEIRA