Banca de QUALIFICAÇÃO: CHRISTIANE DE ARAUJO NOBRE

Uma banca de QUALIFICAÇÃO de DOUTORADO foi cadastrada pelo programa.
STUDENT : CHRISTIANE DE ARAUJO NOBRE
DATE: 28/01/2026
TIME: 09:00
LOCAL: https://meet.google.com/mbk-grkb-bmd
TITLE:

Neuromorphic Network-Based Hardware Architectures for Hyperspectral Image Classification

KEY WORDS:

Computer Vision, Neuromorphic Networks, Hardware Accelerator Spiking Neural Network, Hyperspectral Image.

PAGES: 86
BIG AREA: Ciências Exatas e da Terra
AREA: Ciência da Computação
SUBÁREA: Sistemas de Computação
SPECIALTY: Hardware
SUMMARY:

The growing increase in data volume and demands for high-performance processing

in modern applications, especially those running at the edge of the network (edge

computing), has posed significant challenges to traditional computing architectures,

which often have limitations related to energy consumption, latency, and scalability.

In the field of computer vision, these limitations become even more significant, since

large flows of information need to be processed under severe resource constraints.

In this scenario, neuromorphic computing emerges as a promising approach,

reproducing event-driven processing, distributed memory mechanisms, and

communication through discrete pulses of the human brain. As the main model of

this paradigm, Spiking Neural Networks (SNNs) have gained prominence for being

particularly suitable for computer vision applications in embedded and edge systems,

exploiting the temporal sparsity and binary encoding of spikes, which enables

computationally efficient solutions. Nevertheless, the potential of SNNs can be fully

exploited through the use of dedicated hardware accelerators capable of meeting

requirements such as performance, power consumption, and latency. Given the

above, this work proposes a hardware accelerator based on SNNs for hyperspectral

image (HSI) classification. To achieve this goal, a comprehensive systematic review

of the literature on neural network architectures applied in this context was

conducted. Despite existing studies, no research was identified on hardwareaccelerators for SNNs aimed at HSI processing. The proposed model was

implemented in VHDL, and the Indian Pines dataset was used to evaluate the

structure, assessing performance, accuracy, and hardware resource usage,

comparing it to an accelerator based on CNN-1D architecture. Thus, this work

proposes as a contribution the implementation, testing, and validation of a hardware

accelerator based on SNN architecture, applied to HSIs, capable of offering a

balance between computation time, accuracy, and hardware resource usage.

COMMITTEE MEMBERS:
Presidente - 1694485 - MARCIO EDUARDO KREUTZ
Interna - 1882699 - MONICA MAGALHAES PEREIRA
Externo à Instituição - MATEUS RUZIG - UFSM