LP-P2IP: A low power consumption P2IP implementation using FPGA partial reconfiguration.
Keywords: FPGA, Dynamic Partial Reconfiguration, video processing, real time.
This work uses as its basis the P2IP architecture, which consists of a coarse grain
reconfigurable (runtime) architecture with low latency, applied to real time image processing.
This architecture has been validated in FPGA (Possa 2013), being implemented
with some basic image processing algorithms, such as Canny Edge Detection and Harris
Corner Detection. The aim of the present work is to enlarge the architecture functionality
through Dynamic Partial Reconfiguration, which consists in dividing the chip area in two
regions: a static and a dynamic one. The latter can be reprogrammed without resetting
the whole system. It leads to a lower dynamic energy consumption, a relevant feature if
the system is battery powered. The variables that will be used to validate the system are
the consumption, latency and maximum operating frequency.