Analytical modeling for performance prediction of parallel applications in symmetric architectures considering variations in the data access delay
Analytical modeling, Performance Modeling, Parallel Systems, Data Access Delay, Speedup, Memory Wall
Several analytical models created since Amdahl's pioneering work have explored aspects such as variation in the size of the problem, memory size, communication overhead, and synchronization overhead, but delays in accessing data are considered constant. However, such delays can vary, for example, according to the number of cores used, the relationship between processor and memory frequencies, and the problem's size. Given different problem sizes and the large number of possible configurations of operational frequency and number of cores than current architectures can offer, speedup models suitable for describing such variations among these configurations are quite desirable for offline or online scheduling decisions. A new analytical performance model that considers variations in the average data access delay to describe the limiting effect of the memory wall in parallel applications in homogeneous shared memory architectures is presented in this thesis. The experimental results indicate that the proposed modeling captures the application's behavior well. Besides, we show that considering parameters that reflect the applications' intrinsic characteristics, the proposal presented in this work has significant advantages over statistical models such as those based on machine learning. Our experiments also show that conventional machine learning modeling may need about an order of magnitude more measurements than the proposed model to achieve the same level of precision achieved by the proposed model.