Python Bytecode execution in FPGA
Python; virtual machine; bytecode; scalability.
This work proposes executing Python bytecode directly on an FPGA via a dedicated, synthesizable virtual machine (VM) in Verilog. Unlike HLS-based flows or hardware DSLs, the approach preserves the developer experience: CPython-generated bytecode is consumed by a stack-based microarchitecture, requiring no HDL expertise from the end user. Beyond the VM itself, we investigate the solution’s hardware scalability; that is, scaling the VM to multiple threads directly in hardware to leverage the FPGA’s intrinsic parallelism while removing the GIL. As a proof of concept, we implemented a subset of opcodes and a UART I/O path, evaluated on a Basys 3 (Artix-7). Results show functional compatibility with CPython for the supported subset and indicate promising performance with low resource usage and energy per operation. Expected contributions are: (i) a synthesizable Python VM that executes native bytecode; and (ii) a hardware scalability scheme for multi-threaded execution.