Parallel implementation of genetic algorithm on FPGA
FPGA, Genetic Algorithm, Hardware, Embedded system
This project proposes a parallel implementation of a genetic algorithm (GA) on eld-programmable
gate array (FPGA). Results associated with the processing time and area occupancy (in FPGA) for various
population size are analyzed. Studies concerning the accuracy of the GA response for the optimization problem
using the square function, were also analyzed for the hardware implementation. The project was developed using
the System Generator software (Xilinx development platform) and the Virtex-6 xc6vcx240t 11156 FPGA.