Fault Tolerant Hybrid Processing Architecture for Nanosatellites
CubeSat, FPGA, Hybrid Processing, PULP Architecture, RISC-V.
Currently, the growing demand for on-board processing capacity has stimulated research regarding the use of FPGAs (Field-Programmable Gate Arrays) and systems on chip in CubeSats. However, the constraints concerning mass, size and power, as well as the radiation present in the space environment, are challenges that must be overcome during design of missions with these satellites. Over the years, several processors have been developed based on different instruction set architectures and applying radiation tolerance techniques. Recent papers have analyzed reliability and performance of RISC-V processors in space missions. Although, one verifies a shortage of publications on the application of RISC-V cores to FPGAs for the use in CubeSats. In this context, this work presents a fault-tolerant hybrid processing architecture for application in nanosatellites. The proposed architecture is based on RISC-V cores interconnected with a reconfigurable logic region where a hardware acceleration module will be developed. Thus, one seeks to contribute with an architecture capable of providing high processing capacity and low energy consumption. For the implementation, commercial FPGAs and the AMBA AXI on-chip communication protocol will be used. Furthermore, to validate the proposed architecture, hardware acceleration algorithms for orbit determination and attitude control will be implemented, such as the Kalman Filter.