Proposal of Q-learning Reinforcement Learning Technique in FPGA
FPGA, Q-learning, Reinforcement Learning, Hardware.
Q-learning is a off-policy reinforcement learning technique which has as main advantage the possibility of obtaining an optimal policy interacting with an unknown model environment. This work proposes a parallel fixed-point Q-learning algorithm architecture, implemented in FPGA. Fundamental to this approach is optimize system processing time. Convergence results are presented. The processing time and occupied area were analyzed for different scenarios and various fixed point formats. Architecture implementation details were featured. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.