FPGA hardware implementation for the Q-learning Reinforcement Learning
FPGA, Q-learning, Reinforcement Learning, Hardware.
This paper proposes a parallel implementation of a Q-learning on field-programmable gate array (FPGA). Results associated with the processing time and area occupancy (in FPGA) for various population size are analyzed. Studies concerning the accuracy of the Q-learning response, were also analyzed for the hardware implementation. The project was developed using the System Generator software (Xilinx development platform) and the Virtex-6 xc6vcx240t 1ff1156 FPGA.