Banca de DEFESA: MAILSON RODRIGUES DE MEDEIROS GUIMARAES

Uma banca de DEFESA de MESTRADO foi cadastrada pelo programa.
STUDENT : MAILSON RODRIGUES DE MEDEIROS GUIMARAES
DATE: 31/01/2025
TIME: 09:00
LOCAL: meet.google.com/vpc-szad-teb
TITLE:

HARS1DE: Hardware Architecture for 1D-CNN Processing at the Edge

KEY WORDS:

Edge computing, Hardware architecture, Machine learning, Convolutional neural networks, remote sensing.

PAGES: 90
BIG AREA: Ciências Exatas e da Terra
AREA: Ciência da Computação
SUBÁREA: Sistemas de Computação
SPECIALTY: Hardware
SUMMARY:

There is a trend toward using the cloud computing paradigm, where resources, storage, and information processing are carried out in so-called "clouds" managed by providers. This paradigm is leveraged, for instance, to apply machine learning algorithms to large volumes of data. Conversely, there is the edge computing paradigm, where this processing load is transferred closer to where the data is generated (at the network edge). Investment by technology companies in this type of computing and its techniques has been growing, as it can offer advantages, such as reduced processing latency, energy consumption, and resource demands that may not always be available in the cloud. Similarly to cloud computing, it is possible to apply predictive machine learning models at the edge, where hardware architectures dedicated to accelerating these processes can be employed. Thus, this work's main objective is to implement, test, and validate a hardware architecture capable of accelerating the computation of 1D-CNNs, including pooling, activation, and dense layers, where performance metrics, accuracy, and hardware resource utilization are analyzed. Two representations of the architecture were developed to obtain the results: one in VHDL, synthesized for FPGA to get results regarding hardware resource allocation and timing, and another in Python, a high-level abstraction language, to obtain quicker results on the architecture's behavior during longer processes, such as the computation of an entire neural network. The results were obtained by applying the architecture in remote sensing, specifically for pixel classification in hyperspectral images. The neural network used was a simplified version of previous works to facilitate porting to hardware. In addition to being reconfigurable in the context of FPGAs, the resulting architecture exhibits adaptable behavior depending on the type of neural network layer being processed. Furthermore, it proved scalable, allowing increasing the number of processing elements, thus enhancing the degree of parallelism in operations.

COMMITTEE MEMBERS:
Presidente - 1694485 - MARCIO EDUARDO KREUTZ
Interna - 1882699 - MONICA MAGALHAES PEREIRA
Externo ao Programa - 1837240 - MARCELO AUGUSTO COSTA FERNANDES - UFRNExterno à Instituição - CESAR ALBENES ZEFERINO - UVI