GENERATION OF FAULT-TOLERANT TOPOLOGIES WITH REAL-TIME PACKET DELIVERY CRITERIA
Network on chip, tolopogy, fault tolerance, real time.
The advances in integration capacity of the chips allowed the emergence of systems with several processing cores, with networks-on-chip becoming the main paradigm in the communication between elements of multi-processed systems. Several proposals have emerged in order to meet mainly restrictions of average latency, area, energy consumption. The projects also cover the network architecture, with the generation of topologies that provide optimized performance for specific applications. This work proposes a heuristic for the generation of fault-tolerant topologies capable of delivering real-time and non-real-time packets via an alternative path within the network in the event of a link failure. Exploration always starts from a regular mesh-2D topology and seeks fault-tolerant topologies that are able to deliver as many packages as possible on time. The development of the implementation is based on the NOC42 simulator, making it capable of working with irregular topologies, real-time packages and a routing algorithm based on a routing table.