An AI based Tool for Networks-on-Chip Design Space Exploration 

network-on-chip, artificial intelligence, design space exploration. 

With the increasing number of cores in Systems on Chip (SoCs), bus architectures have suffer some limitations regarding performance. As applications demand more bandwidth and lower latencies, busses could not comply with such requirements due to longer wires and increased capacitancies. Facing this scenario, Networks-on-Chip (NoCs) emerged as a way to overcome limitations found in bus-based systems. NoCs are composed of a set routers and communication links. Each component has its own characteristics. Fully ex- ploring all possible NoC characteristics settings is unfeasible due to the huge design space to cover. Therefore, some methods to speed up this process are needed. In this work we propose the usage of Artificial Intelligence techniques to optimize NoC architectures. This is accomplished by developing an AI based tool to explore the design space in terms of latency prediction for different NoC components configuration. Up to now, nine classifiers were evaluated. To evaluate the tool tests were performed on Audio/Video applications with two traffic patterns, Perfect Shuffle and Matrix Transpose, with four different com- munication requirements. The preliminaries results show an accuracy up to 85% using a Decision Tree to predict latency values.