Design space exploration for optmized irregular topology Networks on Chip: The UTNoC.

Network on chip, Irregular topology, Design space exploration. 

During the design of multiprocessor architectures, the design space exploration step may be aided by tools that assist and accelerate this process. The project of architectures whose communications are based on Networks-on-Chip (NoCs), usually relies on regular topologies, disregarding a possible irregularity in the communication pattern between the interconnected elements. The present work proposes an irregular topology chip network, capable of having good performance (close to the performance of a network connected according to the application graph), through a communication process based on routing tables. The work proposes also a high-level exploration tool using Genetic Algorithm, able to find UTNoC networks with reduced number of connections, and assisting in the design decisions of these networks. Results obtained show that is possible to obtain UTNoC networks with performances close to the performance of networks connected according to the graphs of their applications, and with a reduction in the number of connections of up to 54%, representing a significant reduction of area and energy consumption.