Banca de QUALIFICAÇÃO: CELESTINO ANTÓNIO RAPOSO

Uma banca de QUALIFICAÇÃO de MESTRADO foi cadastrada pelo programa.
STUDENT : CELESTINO ANTÓNIO RAPOSO
DATE: 21/11/2025
TIME: 10:00
LOCAL: meet.google.com/xcs-cqom-nph
TITLE:

Design and Optimization of RISC-V Processor for Use in Chiplets for Integration into Nanosatellites

KEY WORDS:

RISC-V, Chiplets, Nanosatellites, and Fault Tolerance

PAGES: 80
BIG AREA: Ciências Exatas e da Terra
AREA: Ciência da Computação
SUBÁREA: Sistemas de Computação
SUMMARY:

This work proposes and evaluates the design and optimization of a modular RISC-V architecture, focusing on its integration through chiplets for application in nanosatellites. The growing use of small-scale space platforms, such as CubeSats, has driven the search for computing solutions that combine low power consumption, reduced physical space, and high architectural flexibility. In this context, the open RISC-V architecture stands out as a viable alternative by enabling extensibility and customization, while chiplet technology offers a modular integration model that can support the development of heterogeneous and scalable systems. The research encompasses the modeling, implementation, and analysis of an optimized RISC-V core for embedded systems, chiplet-compatible integration, as well as low-cost fault tolerance techniques to ensure reliability without compromising area and energy consumption, a critical factor in small-scale space missions. Simulation experiments and performance analyses are conducted to assess the impact of modularity on the final design. It is expected that the resulting architecture will contribute to the advancement of open and modular platforms applicable to nanosatellites, providing a solid foundation for future physical implementations on FPGA and integration into real space missions.

 

COMMITTEE MEMBERS:
Presidente - 1882699 - MONICA MAGALHAES PEREIRA
Interno - 1694485 - MARCIO EDUARDO KREUTZ
Externo à Instituição - SILVIO ROBERTO FERNANDES DE ARAUJO